FIG. 1 illustrates a conventional pulse width modulation (PWM) regulator. The regulator (10) comprises a variable delay generator (40), an inverter (42), and an AND gate (44). The variable delay generator (40) received a dischg signal (138) and an up_down_ctrl signal (132), as input, and outputs a comp_out signal (136). The AND gate (44) receives a clock signal (11) and an inverted comp_out signal as inputs.
Assuming a 50—50 duty clock cycle, the comp_out signal (136) is low at the beginning of the cycle. When the clock signal (11) goes high, the output (12) goes high. Once the comp_out signal (136) goes high, the AND gate (44) brings the output (12) low. Thus, the width of the high pulse is controlled by the delay between the clock signal (11) going high and the comp_out signal (136) going high.
FIG. 2 illustrates a conventional variable delay generator of the PWM regulator (10). The generator (40) comprises a charge pump (50) and a voltage comparator circuit (55). A “charge pump”, as used in this specification, refers to a circuit comprising a relatively large capacitor whose voltage is moved up or down by injection of a relatively small positive or negative current. The charge pump (50) comprises transistors, M1–M7 (104–116), and a filter capacitor C1 (120). Transistors M1–M5 (104–112) are matched transistors that form a group of current mirrors. A small current (represented by the current source 102) is produced in M2 (106) and M5 (112). These currents are gated by M6 (114) and M7 (116). When the up_down_ctrl signal (132), is high, M6 (114) is “off” and M7 (116) is “on”. This pulls a small current from C1 (120), thus the voltage at node pgate drops slowly. Conversely, when the up_down_ctrl signal (132) is low, M6 (114) is “on” and M7 (116) is “off”, and the current flows from VDD into C1 (120). The voltage on node pgate (130) thus rises slowly. Therefore, the up_down_ctrl signal (132) is translated into a small change in the charge pump's node output.
The voltage comparator circuit (55) comprises a transistor M8 (118), a capacitor C2 (122), a reset circuit represented by transistor M9 (124), and a comparator represented by voltage sources (126 and 128). The voltage comparator circuit (55) uses the voltage on node pgate (130) to produce a current related to that voltage and translates it into a delay time. The gate of M8 (118) is connected to node pgate (130) such that an increase in the voltage on node pgate (130) causes a reduction in the current that flows into C2 (122). A decrease in the voltage on node pgate (130) increases the current that flows into C2 (122). The current in C2 (122) thus rises at a rate proportional to the current in M8 (118). The comparator detects when the voltage at node ramp (134) reaches a predefined level and generates the comp_out signal (136). The dischg signal (138) resets the voltage at node ramp (134). Once the dischg signal (138) goes low, the voltage at node ramp (134) will begin to rise again. In this way, a pulse may be produced at the output (12) whose width is dependent on the voltage on node pgate (130). If the voltage on node pgate (130) is close to VDD, such that there is very little current in M8 (118), the node ramp (134) will not rise at all. As M8 (118) conducts more current, the rise time on node ramp (134) is reduced, and the comp_out signal (136) goes high with little delay. The output (12) goes low once more when the dischg signal (138) is asserted. In this manner, the voltage at node pgate (130) controls the width of the output pulse.
However, the regulator (10) is prone to the “saturation condition”, where the voltage at the node pgate (130) undershoots or overshoots the target voltage. In the regulator (10), the dischg signal (138) is a clock signal with a 50% duty cycle. When the dischg signal (138) is high, the node ramp (134) is held low and the regulator output (12) is also low. During the other half of the cycle, when the dischg signal (138) is low, the voltage on node ramp (134) may rise. If it rises too slowly, such that the voltage on node ramp (134) does not reach the comparator trip point before the dischg signal goes high, there will be no pulse on the output. This will happen if the voltage on node pgate (130) is greater than approximately VDD-Vt, where Vt is the threshold voltage of M8 (118). However, if the up_down_ctrl signal (132) remains low, the charge pump (50) will continue to pull up the voltage on node pgate (130) until it reaches VDD. This is an overshoot condition. When the up_down_ctrl signal (132) goes high again, the voltage on node pgate (130) will take a relatively long time to reach VDD-Vt, when it will begin affecting pulse width. The time during which node pgate (130) is dropping to the voltage at which it affects operation represents a period when the regulator (10) does not respond to the input signal.
Similarly, the voltage at node pgate (130) can fall too far. In this case, the comparator output will go high immediately and the output pulse (12) will be essentially unmodulated. However, the voltage on node pgate (130) can continue to fall, creating an undershoot condition. Both overshoot and undershoot conditions compromise the performance and reliability of the regulator (10).
Accordingly, there exists a need for a PWM regulator which minimizes undershoot and overshoot conditions. The present invention addresses such a need.